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Feature request #290
openImplement FIFO
Start date:
01/06/2023
Due date:
01/10/2023 (over 2 years late)
% Done:
100%
Estimated time:
3:00 h
Spent time:
Description
Implement single-clock, synchronous FIFO based on the DP-DC BRAM.
Testbench
Documentation
Updated by François Cerbelle over 2 years ago
- Blocked by Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module added
Updated by François Cerbelle over 2 years ago
- Start date set to 01/05/2023
- Estimated time changed from 2:00 h to 5:00 h
Updated by François Cerbelle over 2 years ago
- Description updated (diff)
- % Done changed from 0 to 70
Updated by François Cerbelle over 2 years ago
- Status changed from En cours to Résolu
- % Done changed from 80 to 100
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