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Hours: 25:50

Date User Activity Issue Comment Hours
04/11/2023 François Cerbelle Développement Evolution #302: Design the first stage of power supply 12V −> 5.5V Applied in changeset commit:hwredis|6eeec995ef51a83bc7d26ef51198a14d8307bb7f. 2:00 Actions
03/27/2023 François Cerbelle Développement Anomalie #316: Replace the NTMD3P03 dual PMOS with a FDS4935BZ because of thermal dissipation under 2A Applied in changeset commit:hwredis|702b4fad351df37918039ce13a6a440c3b6cd430. 0:15 Actions
03/16/2023 François Cerbelle Développement Anomalie #305: PowerSourceAutoSwitch: Update all components properties in schematic/PCB/BOM Applied in changeset commit:hwredis|a7b641a27447fa3775b12e0762bc6f4d7f69052d. 0:15 Actions
03/16/2023 François Cerbelle Développement Anomalie #306: PowerSourceAutoSwitch: Fix Dual-NMOS footprint Applied in changeset commit:hwredis|33394267c1ed7eb3e67896e1b0c630359f3a9f01. 0:15 Actions
03/01/2023 François Cerbelle Développement Evolution #302: Design the first stage of power supply 12V −> 5.5V 12V/5V5 DC/DC converter design started 2:00 Actions
02/26/2023 François Cerbelle Développement Feature request #303: Design the power switching between PCIe and ATX/XT30 Applied in changeset commit:hwredis|da6450a5992c83448ded069353b50fca87f0393a. 2:00 Actions
02/12/2023 François Cerbelle Développement Evolution #302: Design the first stage of power supply 12V −> 5.5V Chose values and components for 12V-5V5 converter 0:30 Actions
02/11/2023 François Cerbelle Développement Evolution #302: Design the first stage of power supply 12V −> 5.5V hgignore update, PwrSwitching and 12-5 power 1:00 Actions
02/09/2023 François Cerbelle Développement Evolution #302: Design the first stage of power supply 12V −> 5.5V 1:00 Actions
01/14/2023 François Cerbelle Conception Evolution #298: Migrate design details from the documents to the wiki 0:15 Actions
01/11/2023 François Cerbelle Conception Evolution #298: Migrate design details from the documents to the wiki 0:15 Actions
01/11/2023 François Cerbelle Développement Anomalie #297: Make async reset safe regarding clock rises Applied in changeset commit:hwredis|aebf822b36260c7114dbefbc9df452d9914b9ae7. 0:15 Actions
01/10/2023 François Cerbelle Développement Evolution #295: Rename rediscore->gateware, redissoft->firmware, redispcb->hardware, FPGARedis->hakeva Applied in changeset commit:hwredis|bcd1a8ef29a1400faa6defbba2950458548a66f8. 0:15 Actions
01/10/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|d098e312f5dac14d40d5302f023fb42fa9491700. 1:30 Actions
01/10/2023 François Cerbelle Développement Evolution #294: Move all Verilog parameters in a configuration file to include Applied in changeset commit:hwredis|f773e9403ae169fcaabd7b4032f023c5fecde16c. 0:30 Actions
01/09/2023 François Cerbelle Développement Evolution #292: Use Active Low for control signals for better noise tolerance and ensure reset is active at powerup Applied in changeset commit:hwredis|8fb3d1013aa8daf16a099bae102e5d0944a9be40. 1:00 Actions
01/09/2023 François Cerbelle Développement Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module Applied in changeset commit:hwredis|387cbfc7e023931014398c8b27f33e32e6d345f8. 3:00 Actions
01/08/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|2146433c51b8ef6a78fd22b728b6c246a277d95c. 0:30 Actions
01/08/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|3816be32c567428737f8a9e3cfea77fde30907b8. 0:30 Actions
01/07/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|8fc4a10296f72449c2695c3f52911d78437629cb. 0:45 Actions
01/07/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|317eef1019fad8c97ccb9a44a428b031a179412f. 1:30 Actions
01/07/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|0918c6feec8b61c9fe59ad29295fc3c6b4ed825a. 0:15 Actions
01/06/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|7cb5201bdf952c5f2e87f2e8e587401dd035da11. 1:00 Actions
01/05/2023 François Cerbelle Développement Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module Applied in changeset commit:hwredis|92945af441af995b6b2309533c4a16fd4175af3e. 2:00 Actions
01/04/2023 François Cerbelle Développement Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module Applied in changeset commit:hwredis|a19b3211eb7d508caca3e62641a7ec517a274d02. 1:30 Actions
01/04/2023 François Cerbelle Développement Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module Applied in changeset commit:hwredis|a1f87d1c8b228eb6949b67face0f92c4476ec3c6. 0:30 Actions
01/03/2023 François Cerbelle Développement Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module Applied in changeset commit:hwredis|f45729cc6166dae9765f4c400cfd820e52139c67. 0:20 Actions
01/03/2023 François Cerbelle Développement Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module Applied in changeset commit:hwredis|f9172d56207633a357b4e004aa51933a7f758e40. 0:45 Actions
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