Feature request #289
Implement SyncW/AsyncR DP-SC in RAM module
Related issues
Associated revisions
Revision 14:f45729cc6166
(diff)
ram_tb (refs #289 @20m)
Revision 15:a1f87d1c8b22
(diff)
RAM testbench refactored from scratch (Refs #289 @30m)
- Bootstrapped the RAM testbench
Revision 16:a19b3211eb7d
(diff)
RAM testbench refactored from scratch (Refs #289 @1h30m)
- BUGFIX: automatically adjust high-impedance value (z) width to DATA_WIDTH in ram.v
- REFACTOR: completly refactored the ram_tb, implemented a first test serie on OE
Revision 17:92945af441af
(diff)
Completed ram testbench (Closes #289 @2h)
- Refactored ram_tb
- WE test implemented
- Full Write test implemented
- Read test implemented
- Testbench cleanup
- Explicit unconnected ports to avoid warnings
Revision 26:387cbfc7e023
(diff)
Removed i_OE* signals, switched to single-clock and AsyncR in RAM module (Closes #289 @3h)
- Removed OE signals to have read output updated at each clock
- Continuously (Async) assign Read value (blocking infering M9K BRAM blocks)
- Switched to a single-clock dual-port RAM to simplify the design and testbenchs (no cross-domain)
- Refactored the testbench using the FPGA4Students framework
- Updated the top entity to use the updated RAM
- WARN: the testbench selfcheck uses almost the same implementation.
History
Updated by François Cerbelle 11 months ago
- Status changed from Nouveau to Résolu
- % Done changed from 80 to 100
Applied in changeset hwredis|92945af441af995b6b2309533c4a16fd4175af3e.
Updated by François Cerbelle 11 months ago
- Subject changed from Implement dual-port/Dual-clock in RAM module for FIFO to Implement synchronous DP-DC in RAM module for FIFO
Updated by François Cerbelle 11 months ago
Convert the Synchronous SP/SC RAM module in a true Synchronous DP/DC RAM module, write testbench, write documentation
Updated by François Cerbelle 11 months ago
- Subject changed from Implement synchronous DP-DC in RAM module for FIFO to Implement synchronous DP-SC in RAM module
- Status changed from Résolu to En cours
- % Done changed from 100 to 90
Updated by François Cerbelle 11 months ago
- Status changed from En cours to Résolu
- % Done changed from 90 to 100
Applied in changeset hwredis|387cbfc7e023931014398c8b27f33e32e6d345f8.
Updated by François Cerbelle 11 months ago
- Subject changed from Implement synchronous DP-SC in RAM module to Implement SyncW/AsyncR DP-SC in RAM module
RAM implementation, doc update, counter width bugfix...
- Updated header doc with compiler Quartus
- Bugfixed bogus filenames in header docs
- Added missing header documentations
- Bugfixed the counter width
- Renamed RAM module signals
- Made the 7-seg dots blink (debug purpose)
- Implemented a true dual-port, dual-clock, synchronous RAM (Refs #289 @45m)
- Bootstrapped the RAM testbench