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Feature request #289

Implement SyncW/AsyncR DP-SC in RAM module

Added by François Cerbelle 5 months ago. Updated 5 months ago.

Status:
Résolu
Priority:
Normal
Target version:
Start date:
01/02/2023
Due date:
01/05/2023
% Done:

100%

Estimated time:
1.00 h
Spent time:

Related issues

Blocks Feature request #290: Implement FIFORésolu01/06/202301/10/2023

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Associated revisions

Revision 12:f9172d562076 (diff)
Added by François Cerbelle 5 months ago

RAM implementation, doc update, counter width bugfix...
- Updated header doc with compiler Quartus
- Bugfixed bogus filenames in header docs
- Added missing header documentations
- Bugfixed the counter width
- Renamed RAM module signals
- Made the 7-seg dots blink (debug purpose)
- Implemented a true dual-port, dual-clock, synchronous RAM (Refs #289 @45m)
- Bootstrapped the RAM testbench

Revision 14:f45729cc6166 (diff)
Added by François Cerbelle 5 months ago

ram_tb (refs #289 @20m)

Revision 15:a1f87d1c8b22 (diff)
Added by François Cerbelle 5 months ago

RAM testbench refactored from scratch (Refs #289 @30m)
- Bootstrapped the RAM testbench

Revision 16:a19b3211eb7d (diff)
Added by François Cerbelle 5 months ago

RAM testbench refactored from scratch (Refs #289 @1h30m)
- BUGFIX: automatically adjust high-impedance value (z) width to DATA_WIDTH in ram.v
- REFACTOR: completly refactored the ram_tb, implemented a first test serie on OE

Revision 17:92945af441af (diff)
Added by François Cerbelle 5 months ago

Completed ram testbench (Closes #289 @2h)
- Refactored ram_tb
- WE test implemented
- Full Write test implemented
- Read test implemented
- Testbench cleanup
- Explicit unconnected ports to avoid warnings

Revision 26:387cbfc7e023 (diff)
Added by François Cerbelle 5 months ago

Removed i_OE* signals, switched to single-clock and AsyncR in RAM module (Closes #289 @3h)
- Removed OE signals to have read output updated at each clock
- Continuously (Async) assign Read value (blocking infering M9K BRAM blocks)
- Switched to a single-clock dual-port RAM to simplify the design and testbenchs (no cross-domain)
- Refactored the testbench using the FPGA4Students framework
- Updated the top entity to use the updated RAM
- WARN: the testbench selfcheck uses almost the same implementation.

History

#1

Updated by François Cerbelle 5 months ago

#2

Updated by François Cerbelle 5 months ago

  • Estimated time set to 1.00 h
#3

Updated by François Cerbelle 5 months ago

  • Tracker changed from Evolution to Feature request
#4

Updated by François Cerbelle 5 months ago

  • % Done changed from 0 to 70
#5

Updated by François Cerbelle 5 months ago

  • % Done changed from 70 to 80
#6

Updated by François Cerbelle 5 months ago

  • Status changed from Nouveau to Résolu
  • % Done changed from 80 to 100
#7

Updated by François Cerbelle 5 months ago

  • Due date set to 01/05/2023
#8

Updated by François Cerbelle 5 months ago

  • Subject changed from Implement dual-port/Dual-clock in RAM module for FIFO to Implement synchronous DP-DC in RAM module for FIFO
#9

Updated by François Cerbelle 5 months ago

Convert the Synchronous SP/SC RAM module in a true Synchronous DP/DC RAM module, write testbench, write documentation

#10

Updated by François Cerbelle 5 months ago

  • Subject changed from Implement synchronous DP-DC in RAM module for FIFO to Implement synchronous DP-SC in RAM module
  • Status changed from Résolu to En cours
  • % Done changed from 100 to 90
#11

Updated by François Cerbelle 5 months ago

  • Status changed from En cours to Résolu
  • % Done changed from 90 to 100
#12

Updated by François Cerbelle 5 months ago

  • Subject changed from Implement synchronous DP-SC in RAM module to Implement SyncW/AsyncR DP-SC in RAM module
#13

Updated by François Cerbelle 5 months ago

  • Status changed from Résolu to Fermé
#14

Updated by François Cerbelle 5 months ago

  • Status changed from Fermé to Résolu

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