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Feature request #289
openImplement SyncW/AsyncR DP-SC in RAM module
Start date:
01/02/2023
Due date:
01/05/2023 (about 24 months late)
% Done:
100%
Estimated time:
1:00 h
Spent time:
Updated by François Cerbelle almost 2 years ago
- Blocks Feature request #290: Implement FIFO added
Updated by François Cerbelle almost 2 years ago
- Tracker changed from Evolution to Feature request
Updated by François Cerbelle almost 2 years ago
- Status changed from Nouveau to Résolu
- % Done changed from 80 to 100
Applied in changeset hwredis|92945af441af995b6b2309533c4a16fd4175af3e.
Updated by François Cerbelle almost 2 years ago
- Subject changed from Implement dual-port/Dual-clock in RAM module for FIFO to Implement synchronous DP-DC in RAM module for FIFO
Updated by François Cerbelle almost 2 years ago
Convert the Synchronous SP/SC RAM module in a true Synchronous DP/DC RAM module, write testbench, write documentation
Updated by François Cerbelle almost 2 years ago
- Subject changed from Implement synchronous DP-DC in RAM module for FIFO to Implement synchronous DP-SC in RAM module
- Status changed from Résolu to En cours
- % Done changed from 100 to 90
Updated by François Cerbelle almost 2 years ago
- Status changed from En cours to Résolu
- % Done changed from 90 to 100
Applied in changeset hwredis|387cbfc7e023931014398c8b27f33e32e6d345f8.
Updated by François Cerbelle almost 2 years ago
- Subject changed from Implement synchronous DP-SC in RAM module to Implement SyncW/AsyncR DP-SC in RAM module
Updated by François Cerbelle almost 2 years ago
- Status changed from Résolu to Fermé
Updated by François Cerbelle almost 2 years ago
- Status changed from Fermé to Résolu
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