Version 0.1¶This version is the initial version with basic stuffs :
- RedisCore (Verilog/FPGA)
- RAM blocks
- UART input/output 115200bds 8N1
- Command existence validation
- Command arity check
- Arbitrary processing
- RedisService (C/Microcontroller)
- Nothing (yet)
- Hardware (Backplane and daughter PCBs)
- Nothing (yet)
UART for input/output simulation¶
Accept incoming data and forward them, accept forwarded data and send them. The forward and accept design has to be compatible with a network connection design. This UART design is temporary, for tests and has to be replacable by a TCP/IP design.
The goal is to manage real-time background garbage collection and defragmentation. Each used memory block address is stoerd in a memory block pointer table and the IP Blocks only use indirect pointers, address in the memory block table. Thus, a physical memory block can be moved transparently, as long as the address in the block table is changed atomically.
Memory block table entries¶
RAM Block Address and RAM Block size
- Allocate a block
- Free a block
The goal is to receive a RESP encoded command from UART and reply to UART.
- Consume (parse) the arity (RESP array size) and first string (RESP array first string)
- Early (before consuming the arguments) return "ERR Command not found" if the command is not in the command table (internal M9K RAM).
- Early return "ERR Wrong arity" if the parsed string count is incompatible with the command retrieved in the command table.
- Find enough consecutive available RAM block allocation table entries accordingly to the arguments count
- Store the arguments in a memory block (internal M9K yet), update the RAM allocation table entries with the address of each argument
- Pass the first RAM allocation entry to the appropriate command circuit block module
- Wait until RDY
- Copy the result string from RAM (design to be specified) to UART