Feature request #290
Implement FIFO
Description
Implement single-clock, synchronous FIFO based on the DP-DC BRAM.
Testbench
Documentation
Related issues
Associated revisions
Revision 21:0918c6feec8b
(diff)
Bootstrapped FIFO testbench (Refs #290 @15m)
- Fixed simulation compilation errors
Revision 22:317eef1019fa
(diff)
Converted FIFO testbench to fpga4students framework (Refs #290 @1h30)
Revision 23:8fc4a10296f7
(diff)
Partially adapted the self-check in FIFO testbench (Refs #290 @45m)
Revision 24:3816be32c567
(diff)
FIFO protection against overwriting or reading stale values (Refs #290 @30m)
Disabled testbench self-check designed for async reads, not applicable with sync reads
Revision 25:2146433c51b8
(diff)
Improved FIFO testbanch selftest (Refs #290 @30m)
Revision 29:d098e312f5da
(diff)
FIFO: Adapted testbench for SC-AR_RAM (Closes #290 @1h30m)...
- ram: i_WE*==z is not supported, added RAM module assertion and doc
- ram_tb: Added test numbers in output
- fifo: Enhanced documentation
- fifo: Ported to use SC-AR RAM module
- fifo: BUGFIX explicitely set a value for RAM:i_WE1
- fifo: Better labels in assertions
- fifo_tb: Added EndOfTest condition and Timeout error
- fifo_tb: Factorized RESET_PULSE in a task
- fifo_tb: w_Empty and w_Full management
- fifo_tb: Factorized FAIL in a task
History
Updated by François Cerbelle 5 months ago
- Blocked by Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module added
Updated by François Cerbelle 5 months ago
- Start date set to 01/05/2023
- Estimated time changed from 2.00 h to 5.00 h
Updated by François Cerbelle 5 months ago
- Estimated time changed from 5.00 h to 3.00 h
Implement dual-port, dual-clock-synchronous FIFO based on the DP-DC BRAM.
Testbench
Documentation
Updated by François Cerbelle 5 months ago
- Description updated (diff)
- % Done changed from 0 to 70
Updated by François Cerbelle 5 months ago
- % Done changed from 70 to 80
Implement Testbench self-check
Updated by François Cerbelle 5 months ago
- Status changed from En cours to Résolu
- % Done changed from 80 to 100
Applied in changeset hwredis|d098e312f5dac14d40d5302f023fb42fa9491700.
FIFO almost implemented (Refs #290 @1h)
- Single clock
- Synchronous