Feature request #290: Implement FIFO - Hakeva - Redmine

Feature request #290

Implement FIFO

Added by François Cerbelle 5 months ago. Updated 5 months ago.

Status:

Résolu

Priority:

Normal

Assignee:

François Cerbelle

Target version:

0.1

Start date:

01/06/2023

Due date:

01/10/2023

% Done:

100%

Estimated time:

3.00 h

Spent time:

6.00 h

Description

Implement single-clock, synchronous FIFO based on the DP-DC BRAM.
Testbench
Documentation

Related issues

Associated revisions

Revision 20:7cb5201bdf95 (diff)
Added by François Cerbelle 5 months ago

FIFO almost implemented (Refs #290 @1h)
- Single clock
- Synchronous

Revision 21:0918c6feec8b (diff)
Added by François Cerbelle 5 months ago

Bootstrapped FIFO testbench (Refs #290 @15m)
- Fixed simulation compilation errors

Revision 22:317eef1019fa (diff)
Added by François Cerbelle 5 months ago

Converted FIFO testbench to fpga4students framework (Refs #290 @1h30)

Revision 23:8fc4a10296f7 (diff)
Added by François Cerbelle 5 months ago

Partially adapted the self-check in FIFO testbench (Refs #290 @45m)

Revision 24:3816be32c567 (diff)
Added by François Cerbelle 5 months ago

FIFO protection against overwriting or reading stale values (Refs #290 @30m)
Disabled testbench self-check designed for async reads, not applicable with sync reads

Revision 25:2146433c51b8 (diff)
Added by François Cerbelle 5 months ago

Improved FIFO testbanch selftest (Refs #290 @30m)

Revision 29:d098e312f5da (diff)
Added by François Cerbelle 5 months ago

FIFO: Adapted testbench for SC-AR_RAM (Closes #290 @1h30m)...
- ram: i_WE*==z is not supported, added RAM module assertion and doc
- ram_tb: Added test numbers in output
- fifo: Enhanced documentation
- fifo: Ported to use SC-AR RAM module
- fifo: BUGFIX explicitely set a value for RAM:i_WE1
- fifo: Better labels in assertions
- fifo_tb: Added EndOfTest condition and Timeout error
- fifo_tb: Factorized RESET_PULSE in a task
- fifo_tb: w_Empty and w_Full management
- fifo_tb: Factorized FAIL in a task