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Feature request #290
openImplement FIFO
Start date:
01/06/2023
Due date:
01/10/2023 (about 24 months late)
% Done:
100%
Estimated time:
3:00 h
Spent time:
Description
Implement single-clock, synchronous FIFO based on the DP-DC BRAM.
Testbench
Documentation
Updated by François Cerbelle almost 2 years ago
- Blocked by Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module added
Updated by François Cerbelle almost 2 years ago
- Blocks Feature request #291: Implement UART added
Updated by François Cerbelle almost 2 years ago
- Tracker changed from Evolution to Feature request
Updated by François Cerbelle almost 2 years ago
- Start date set to 01/05/2023
- Estimated time changed from 2:00 h to 5:00 h
Updated by François Cerbelle almost 2 years ago
- Estimated time changed from 5:00 h to 3:00 h
Implement dual-port, dual-clock-synchronous FIFO based on the DP-DC BRAM.
Testbench
Documentation
Updated by François Cerbelle almost 2 years ago
- Status changed from Nouveau to En cours
Updated by François Cerbelle almost 2 years ago
- Description updated (diff)
- % Done changed from 0 to 70
Updated by François Cerbelle almost 2 years ago
- Start date changed from 01/05/2023 to 01/06/2023
Updated by François Cerbelle almost 2 years ago
- % Done changed from 70 to 80
Implement Testbench self-check
Updated by François Cerbelle almost 2 years ago
- Due date changed from 01/08/2023 to 01/15/2023
Updated by François Cerbelle almost 2 years ago
- Status changed from En cours to Résolu
- % Done changed from 80 to 100
Applied in changeset hwredis|d098e312f5dac14d40d5302f023fb42fa9491700.
Updated by François Cerbelle almost 2 years ago
- Due date changed from 01/15/2023 to 01/10/2023
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