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Feature request #290

open

Implement FIFO

Added by François Cerbelle over 1 year ago. Updated over 1 year ago.

Status:
Résolu
Priority:
Normal
Assignee:
François Cerbelle
Target version:
0.1
Start date:
01/06/2023
Due date:
01/10/2023 (about 16 months late)
% Done:

100%

Estimated time:
3:00 h
Spent time:
6:00 h

Description

Implement single-clock, synchronous FIFO based on the DP-DC BRAM.
Testbench
Documentation

Related issues 2 (2 open — 0 closed)

Blocked by Feature request #289: Implement SyncW/AsyncR DP-SC in RAM moduleRésoluFrançois Cerbelle01/02/202301/05/2023

Actions
Blocks Feature request #291: Implement UARTNouveauFrançois Cerbelle01/11/2023

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