Anomalie #297: Make async reset safe regarding clock rises - Hakeva - Redmine

Anomalie #297

Make async reset safe regarding clock rises

Added by François Cerbelle 5 months ago. Updated 5 months ago.

Status:

Résolu

Priority:

Normal

Assignee:

François Cerbelle

Target version:

Start date:

01/11/2023

Due date:

01/11/2023

% Done:

100%

Estimated time:

Spent time:

Description

see https://www.01signal.com/verilog-design/reset/synchronous-vs-asynchronous/

Associated revisions

Revision 31:aebf822b3626 (diff)
Added by François Cerbelle 5 months ago

Implemented and used async synced reset (Closes #297 @15m)

History

#1

Updated by François Cerbelle 5 months ago

Status changed from Nouveau to Résolu
% Done changed from 0 to 100

Applied in changeset hwredis|aebf822b36260c7114dbefbc9df452d9914b9ae7.

#2

Updated by François Cerbelle 5 months ago

Due date set to 01/11/2023

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