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Anomalie #297

open

Make async reset safe regarding clock rises

Added by François Cerbelle over 1 year ago. Updated over 1 year ago.

Status:
Résolu
Priority:
Normal
Assignee:
François Cerbelle
Target version:
0.1
Start date:
01/11/2023
Due date:
01/11/2023 (about 16 months late)
% Done:

100%

Estimated time:
Spent time:
0:15 h

Description

see https://www.01signal.com/verilog-design/reset/synchronous-vs-asynchronous/

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