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# Project Tracker Status Priority Subject Assignee Updated Target version Estimated time % Done
251 FC005-ElectronicLoad Anomalie Résolu Haut Cleanup schema 07/15/2020 04:54 PM FC005-ElectronicLoad - 1.1 2:00

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252 FC005-ElectronicLoad Anomalie Nouveau Normal Security shutdown if thermistance is shorted or disconnected 07/15/2020 05:18 PM

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254 FC005-ElectronicLoad Anomalie Nouveau Normal Stackable PCB 07/18/2020 12:58 AM FC005-ElectronicLoad - 1.1

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253 FC005-ElectronicLoad Anomalie Résolu Normal Replace ADA4611 with (P)DIP (LM2904?) 07/19/2020 02:15 AM FC005-ElectronicLoad - 1.1

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225 FC005-ElectronicLoad Evolution Nouveau Normal Try to replace SMD components with DIP or through-hole equivalents 07/23/2020 12:36 AM 5:00

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227 FC005-ElectronicLoad Evolution Résolu Normal Protect all connectors against reversed connection 07/23/2020 12:38 AM FC005-ElectronicLoad - 1.1 2:00

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256 FC005-ElectronicLoad Anomalie Résolu Normal Investigate current limiting and thermal runaway in MOSFET with transistors and resistors 07/23/2020 11:51 PM FC005-ElectronicLoad - 1.1

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262 fifo Evolution Nouveau Normal buffer testbench 08/20/2020 01:04 PM fifo - 1.0

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263 fifo Evolution Nouveau Normal waddr testbench 08/20/2020 01:09 PM fifo - 1.0

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264 fifo Evolution Nouveau Normal raddr testbench 08/20/2020 01:09 PM fifo - 1.0

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265 fifo Evolution Nouveau Normal signal testbench 08/20/2020 01:09 PM fifo - 1.0

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266 fifo Evolution Nouveau Normal fifo testbench 08/20/2020 01:09 PM fifo - 1.0

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260 fifo Evolution Nouveau Normal fifo_overflow port in fifo module 08/20/2020 01:12 PM fifo - 1.0 1:00

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259 fifo Evolution Nouveau Normal fifo_full port in fifo module 08/20/2020 01:12 PM fifo - 1.0 1:00

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258 fifo Evolution Nouveau Normal fifo_underflow port in fifo module 08/20/2020 01:12 PM fifo - 1.0 1:00

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261 fifo Evolution Nouveau Normal signal submodule 08/20/2020 01:12 PM fifo - 1.0

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257 fifo Evolution Nouveau Normal fifo_empty port in fifo module 08/20/2020 01:12 PM fifo - 1.0 1:00

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255 FC005-ElectronicLoad Evolution Résolu Normal Fan power from PowerPCB to commandPCB/Relay, back to power PCB 08/23/2020 05:12 PM

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267 FC005-ElectronicLoad Anomalie Nouveau Normal Fix C15/C16 footprints 10/06/2020 04:03 PM FC005-ElectronicLoad - 1.1 0:15

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268 FC005-ElectronicLoad Anomalie Nouveau Haut Fix connection C25/1 with track +5V !!! 10/06/2020 07:49 PM FC005-ElectronicLoad - 1.1 0:15

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280 francois.cerbelle.net Evolution Nouveau Normal Choose a new theme 05/04/2021 07:08 PM

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281 francois.cerbelle.net Feature request Nouveau Normal Include socicons 05/04/2021 07:59 PM

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282 francois.cerbelle.net Feature request Nouveau Normal Customize external links 05/04/2021 07:59 PM

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283 francois.cerbelle.net Feature request Nouveau Normal included images theme 05/04/2021 08:04 PM

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284 francois.cerbelle.net Feature request Nouveau Normal Category page 05/04/2021 08:04 PM

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285 francois.cerbelle.net Feature request Nouveau Normal Tags page or widget 05/04/2021 08:04 PM

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286 francois.cerbelle.net Feature request Nouveau Normal Menu with pages 05/04/2021 08:05 PM

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287 francois.cerbelle.net Feature request Nouveau Normal Google analytics 05/04/2021 08:05 PM

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288 francois.cerbelle.net Feature request Nouveau Normal Multi-languages 05/06/2021 05:42 PM

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289 Hakeva Feature request Résolu Normal Implement SyncW/AsyncR DP-SC in RAM module François Cerbelle 01/10/2023 09:30 AM Hakeva - 0.1 1:00

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296 Hakeva Evolution Nouveau Normal Change project id in Redmine and in Hg François Cerbelle 01/11/2023 08:08 AM Hakeva - 0.1

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290 Hakeva Feature request Résolu Normal Implement FIFO François Cerbelle 01/11/2023 08:38 AM Hakeva - 0.1 3:00

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292 Hakeva Evolution Résolu Normal Use Active Low for control signals for better noise tolerance and ensure reset is active at powerup François Cerbelle 01/11/2023 11:21 PM Hakeva - 0.1 2:00

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293 Hakeva Evolution Résolu Normal Switch everything to single clock domain in order to keep implementation simple for now François Cerbelle 01/11/2023 11:22 PM Hakeva - 0.1 2:00

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294 Hakeva Evolution Résolu Normal Move all Verilog parameters in a configuration file to include François Cerbelle 01/11/2023 11:22 PM Hakeva - 0.1 0:15

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295 Hakeva Evolution Résolu Normal Rename rediscore->gateware, redissoft->firmware, redispcb->hardware, FPGARedis->hakeva François Cerbelle 01/11/2023 11:23 PM Hakeva - 0.1 5:00

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297 Hakeva Anomalie Résolu Normal Make async reset safe regarding clock rises François Cerbelle 01/11/2023 11:23 PM Hakeva - 0.1

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299 Hakeva Evolution Nouveau Normal Create a clean clock François Cerbelle 01/12/2023 08:47 AM Hakeva - 0.1 1:00

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298 Hakeva Evolution Résolu Normal Migrate design details from the documents to the wiki François Cerbelle 01/14/2023 11:03 AM Hakeva - 0.1 0:30

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300 Hakeva Evolution Nouveau Normal Rethink desing to have a FPGA PCB PCI formfactor compatible with PC and backplane François Cerbelle 01/15/2023 09:05 PM Hakeva - 0.1

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301 Hakeva Evolution Nouveau Normal Update core design for a PCI card with DMA François Cerbelle 01/16/2023 08:35 AM Hakeva - 0.1 5:00

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291 Hakeva Feature request Nouveau Normal Implement UART François Cerbelle 02/09/2023 09:05 AM Hakeva - 0.1 5:00

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303 Hakeva Feature request Résolu Normal Design the power switching between PCIe and ATX/XT30 François Cerbelle 02/26/2023 08:33 PM Hakeva - 0.1 2:00

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305 Hakeva Anomalie Résolu Normal PowerSourceAutoSwitch: Update all components properties in schematic/PCB/BOM François Cerbelle 03/16/2023 07:59 PM Hakeva - 0.1 0:30

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306 Hakeva Anomalie Résolu Normal PowerSourceAutoSwitch: Fix Dual-NMOS footprint François Cerbelle 03/16/2023 08:00 PM Hakeva - 0.1 0:15

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307 Hakeva Feature request Nouveau Normal Add JTAG connector François Cerbelle 03/22/2023 08:44 AM Hakeva - 0.1

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308 Hakeva Feature request Nouveau Normal Add SPI Flash François Cerbelle 03/22/2023 08:44 AM Hakeva - 0.1

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309 Hakeva Feature request Nouveau Normal Add DDR3 François Cerbelle 03/22/2023 08:44 AM Hakeva - 0.1

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310 Hakeva Feature request Nouveau Normal Add eMMC François Cerbelle 03/22/2023 08:45 AM Hakeva - 0.1

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311 Hakeva Feature request Nouveau Normal Add PCIe connection François Cerbelle 03/22/2023 08:45 AM Hakeva - 0.1

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