Dual channel, single clock FIFO¶

With data_width and addr_width parameters.
Can be used to implement any kind of simple buffer
The buffer infers to M9K memory cells in Quartus2/CycloneIV

• http://electrosofts.com/verilog/fifo.html
• https://www.fpga4student.com/2017/01/verilog-code-for-fifo-memory.html