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# Project Tracker Status Priority Subject Assignee Updated Target version Estimated time % Done
313 Hakeva Feature request Nouveau Normal Add 10G SPF+ François Cerbelle 03/22/2023 08:45 AM Hakeva - 0.1

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312 Hakeva Feature request Nouveau Normal Add 10/100/1000 RJ45 François Cerbelle 03/22/2023 08:45 AM Hakeva - 0.1

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311 Hakeva Feature request Nouveau Normal Add PCIe connection François Cerbelle 03/22/2023 08:45 AM Hakeva - 0.1

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310 Hakeva Feature request Nouveau Normal Add eMMC François Cerbelle 03/22/2023 08:45 AM Hakeva - 0.1

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309 Hakeva Feature request Nouveau Normal Add DDR3 François Cerbelle 03/22/2023 08:44 AM Hakeva - 0.1

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308 Hakeva Feature request Nouveau Normal Add SPI Flash François Cerbelle 03/22/2023 08:44 AM Hakeva - 0.1

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307 Hakeva Feature request Nouveau Normal Add JTAG connector François Cerbelle 03/22/2023 08:44 AM Hakeva - 0.1

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306 Hakeva Anomalie Résolu Normal PowerSourceAutoSwitch: Fix Dual-NMOS footprint François Cerbelle 03/16/2023 08:00 PM Hakeva - 0.1 0:15

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305 Hakeva Anomalie Résolu Normal PowerSourceAutoSwitch: Update all components properties in schematic/PCB/BOM François Cerbelle 03/16/2023 07:59 PM Hakeva - 0.1 0:30

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303 Hakeva Feature request Résolu Normal Design the power switching between PCIe and ATX/XT30 François Cerbelle 02/26/2023 08:33 PM Hakeva - 0.1 2:00

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302 Hakeva Evolution Résolu Normal Design the first stage of power supply 12V −> 5.5V François Cerbelle 04/11/2023 10:25 PM Hakeva - 0.1 5:00

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301 Hakeva Evolution Nouveau Normal Update core design for a PCI card with DMA François Cerbelle 01/16/2023 08:35 AM Hakeva - 0.1 5:00

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300 Hakeva Evolution Nouveau Normal Rethink desing to have a FPGA PCB PCI formfactor compatible with PC and backplane François Cerbelle 01/15/2023 09:05 PM Hakeva - 0.1

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299 Hakeva Evolution Nouveau Normal Create a clean clock François Cerbelle 01/12/2023 08:47 AM Hakeva - 0.1 1:00

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298 Hakeva Evolution Résolu Normal Migrate design details from the documents to the wiki François Cerbelle 01/14/2023 11:03 AM Hakeva - 0.1 0:30

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297 Hakeva Anomalie Résolu Normal Make async reset safe regarding clock rises François Cerbelle 01/11/2023 11:23 PM Hakeva - 0.1

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296 Hakeva Evolution Nouveau Normal Change project id in Redmine and in Hg François Cerbelle 01/11/2023 08:08 AM Hakeva - 0.1

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295 Hakeva Evolution Résolu Normal Rename rediscore->gateware, redissoft->firmware, redispcb->hardware, FPGARedis->hakeva François Cerbelle 01/11/2023 11:23 PM Hakeva - 0.1 5:00

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294 Hakeva Evolution Résolu Normal Move all Verilog parameters in a configuration file to include François Cerbelle 01/11/2023 11:22 PM Hakeva - 0.1 0:15

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293 Hakeva Evolution Résolu Normal Switch everything to single clock domain in order to keep implementation simple for now François Cerbelle 01/11/2023 11:22 PM Hakeva - 0.1 2:00

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292 Hakeva Evolution Résolu Normal Use Active Low for control signals for better noise tolerance and ensure reset is active at powerup François Cerbelle 01/11/2023 11:21 PM Hakeva - 0.1 2:00

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291 Hakeva Feature request Nouveau Normal Implement UART François Cerbelle 02/09/2023 09:05 AM Hakeva - 0.1 5:00

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290 Hakeva Feature request Résolu Normal Implement FIFO François Cerbelle 01/11/2023 08:38 AM Hakeva - 0.1 3:00

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289 Hakeva Feature request Résolu Normal Implement SyncW/AsyncR DP-SC in RAM module François Cerbelle 01/10/2023 09:30 AM Hakeva - 0.1 1:00

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288 francois.cerbelle.net Feature request Nouveau Normal Multi-languages 05/06/2021 05:42 PM

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287 francois.cerbelle.net Feature request Nouveau Normal Google analytics 05/04/2021 08:05 PM

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286 francois.cerbelle.net Feature request Nouveau Normal Menu with pages 05/04/2021 08:05 PM

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285 francois.cerbelle.net Feature request Nouveau Normal Tags page or widget 05/04/2021 08:04 PM

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284 francois.cerbelle.net Feature request Nouveau Normal Category page 05/04/2021 08:04 PM

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283 francois.cerbelle.net Feature request Nouveau Normal included images theme 05/04/2021 08:04 PM

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282 francois.cerbelle.net Feature request Nouveau Normal Customize external links 05/04/2021 07:59 PM

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281 francois.cerbelle.net Feature request Nouveau Normal Include socicons 05/04/2021 07:59 PM

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280 francois.cerbelle.net Evolution Nouveau Normal Choose a new theme 05/04/2021 07:08 PM

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255 FC005-ElectronicLoad Evolution Résolu Normal Fan power from PowerPCB to commandPCB/Relay, back to power PCB 08/23/2020 05:12 PM

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252 FC005-ElectronicLoad Anomalie Nouveau Normal Security shutdown if thermistance is shorted or disconnected 07/15/2020 05:18 PM

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250 FC005-ElectronicLoad Anomalie Nouveau Bas Connect RTC interrupt line 07/14/2020 05:41 PM 1:00

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249 FC005-ElectronicLoad Evolution Nouveau Normal ESP8266 connected to FTDI 07/09/2020 06:21 PM

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248 FC005-ElectronicLoad Evolution Nouveau Normal Analog Feedback Zero adjust. RV ? 07/09/2020 06:21 PM

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247 FC005-ElectronicLoad Evolution Nouveau Normal Sense Zero adjust. RV 07/14/2020 12:19 AM

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246 FC005-ElectronicLoad Evolution Nouveau Normal I²C IO extender for keyboard 07/09/2020 06:20 PM

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225 FC005-ElectronicLoad Evolution Nouveau Normal Try to replace SMD components with DIP or through-hole equivalents 07/23/2020 12:36 AM 5:00

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218 FC005-ElectronicLoad Evolution Nouveau Normal High voltage/current on a dedicated support as Backpanel 07/04/2020 12:16 PM 2:00

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207 FC005-ElectronicLoad Anomalie Nouveau Normal FTDI reset 07/04/2020 12:17 PM 2:00

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195 FC005-ElectronicLoad Evolution Résolu Normal Symetric power supply circuit 07/11/2020 02:25 AM 5:00

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152 Puppet Modules Evolution Nouveau Normal download : add mode management François Cerbelle 01/28/2016 07:11 PM 0:30

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151 Puppet Modules Evolution Nouveau Normal download : add group management François Cerbelle 01/28/2016 07:11 PM 0:30

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150 Puppet Modules Evolution Nouveau Normal download : add owner management François Cerbelle 01/28/2016 07:10 PM 0:30

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149 Puppet Modules Evolution Nouveau Normal download : add no-check-certificates management François Cerbelle 01/28/2016 07:10 PM 0:30

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133 Demo VM Evolution Résolu Normal Add JasperEmbedSample to VM François Cerbelle 06/27/2014 06:06 PM

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122 Puppet Modules Anomalie Résolu Haut distcc::params::allowednets cannot contain spaces, it breaks augeas rule in distcc::init.pp François Cerbelle 12/09/2013 03:56 PM 1:00

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