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Hours: 305:52

Project Date User Activity Issue Comment Hours
Hakeva 03/01/2023 François Cerbelle Développement Evolution #302: Design the first stage of power supply 12V −> 5.5V 12V/5V5 DC/DC converter design started 2:00 Actions
Hakeva 02/26/2023 François Cerbelle Développement Feature request #303: Design the power switching between PCIe and ATX/XT30 Applied in changeset commit:hwredis|da6450a5992c83448ded069353b50fca87f0393a. 2:00 Actions
Hakeva 02/12/2023 François Cerbelle Développement Evolution #302: Design the first stage of power supply 12V −> 5.5V Chose values and components for 12V-5V5 converter 0:30 Actions
Hakeva 02/11/2023 François Cerbelle Développement Evolution #302: Design the first stage of power supply 12V −> 5.5V hgignore update, PwrSwitching and 12-5 power 1:00 Actions
Hakeva 02/09/2023 François Cerbelle Développement Evolution #302: Design the first stage of power supply 12V −> 5.5V 1:00 Actions
Hakeva 01/14/2023 François Cerbelle Conception Evolution #298: Migrate design details from the documents to the wiki 0:15 Actions
Hakeva 01/11/2023 François Cerbelle Conception Evolution #298: Migrate design details from the documents to the wiki 0:15 Actions
Hakeva 01/11/2023 François Cerbelle Développement Anomalie #297: Make async reset safe regarding clock rises Applied in changeset commit:hwredis|aebf822b36260c7114dbefbc9df452d9914b9ae7. 0:15 Actions
Hakeva 01/10/2023 François Cerbelle Développement Evolution #295: Rename rediscore->gateware, redissoft->firmware, redispcb->hardware, FPGARedis->hakeva Applied in changeset commit:hwredis|bcd1a8ef29a1400faa6defbba2950458548a66f8. 0:15 Actions
Hakeva 01/10/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|d098e312f5dac14d40d5302f023fb42fa9491700. 1:30 Actions
Hakeva 01/10/2023 François Cerbelle Développement Evolution #294: Move all Verilog parameters in a configuration file to include Applied in changeset commit:hwredis|f773e9403ae169fcaabd7b4032f023c5fecde16c. 0:30 Actions
Hakeva 01/09/2023 François Cerbelle Développement Evolution #292: Use Active Low for control signals for better noise tolerance and ensure reset is active at powerup Applied in changeset commit:hwredis|8fb3d1013aa8daf16a099bae102e5d0944a9be40. 1:00 Actions
Hakeva 01/09/2023 François Cerbelle Développement Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module Applied in changeset commit:hwredis|387cbfc7e023931014398c8b27f33e32e6d345f8. 3:00 Actions
Hakeva 01/08/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|2146433c51b8ef6a78fd22b728b6c246a277d95c. 0:30 Actions
Hakeva 01/08/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|3816be32c567428737f8a9e3cfea77fde30907b8. 0:30 Actions
Hakeva 01/07/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|8fc4a10296f72449c2695c3f52911d78437629cb. 0:45 Actions
Hakeva 01/07/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|317eef1019fad8c97ccb9a44a428b031a179412f. 1:30 Actions
Hakeva 01/07/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|0918c6feec8b61c9fe59ad29295fc3c6b4ed825a. 0:15 Actions
Hakeva 01/06/2023 François Cerbelle Développement Feature request #290: Implement FIFO Applied in changeset commit:hwredis|7cb5201bdf952c5f2e87f2e8e587401dd035da11. 1:00 Actions
Hakeva 01/05/2023 François Cerbelle Développement Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module Applied in changeset commit:hwredis|92945af441af995b6b2309533c4a16fd4175af3e. 2:00 Actions
Hakeva 01/04/2023 François Cerbelle Développement Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module Applied in changeset commit:hwredis|a19b3211eb7d508caca3e62641a7ec517a274d02. 1:30 Actions
Hakeva 01/04/2023 François Cerbelle Développement Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module Applied in changeset commit:hwredis|a1f87d1c8b228eb6949b67face0f92c4476ec3c6. 0:30 Actions
Hakeva 01/03/2023 François Cerbelle Développement Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module Applied in changeset commit:hwredis|f45729cc6166dae9765f4c400cfd820e52139c67. 0:20 Actions
Hakeva 01/03/2023 François Cerbelle Développement Feature request #289: Implement SyncW/AsyncR DP-SC in RAM module Applied in changeset commit:hwredis|f9172d56207633a357b4e004aa51933a7f758e40. 0:45 Actions
mkernel 04/16/2021 François Cerbelle Développement Anomalie #278: define and use DEFAULT_MODULE_PATH 0:15 Actions
FC005-ElectronicLoad 07/23/2020 François Cerbelle Conception Anomalie #256: Investigate current limiting and thermal runaway in MOSFET with transistors and resistors 2:00 Actions
FC005-ElectronicLoad 07/23/2020 François Cerbelle Conception Evolution #227: Protect all connectors against reversed connection 1:00 Actions
FC005-ElectronicLoad 07/23/2020 François Cerbelle Conception Anomalie #256: Investigate current limiting and thermal runaway in MOSFET with transistors and resistors 1:00 Actions
FC005-ElectronicLoad 07/23/2020 François Cerbelle Conception Evolution #225: Try to replace SMD components with DIP or through-hole equivalents 1:00 Actions
FC005-ElectronicLoad 07/19/2020 François Cerbelle Conception Evolution #227: Protect all connectors against reversed connection 0:15 Actions
FC005-ElectronicLoad 07/19/2020 François Cerbelle Conception Anomalie #253: Replace ADA4611 with (P)DIP (LM2904?) 1:00 Actions
FC005-ElectronicLoad 07/14/2020 François Cerbelle Conception Evolution #211: Add debug solder bridges to isolate each pin of each connector 1:00 Actions
FC005-ElectronicLoad 07/14/2020 François Cerbelle Conception Anomalie #232: Resize R18 0:15 Actions
FC005-ElectronicLoad 07/14/2020 François Cerbelle Conception Evolution #230: Convert the whole resistor block use only -12/+12 (no 5V dependency anymore) 1:00 Actions
FC005-ElectronicLoad 07/14/2020 François Cerbelle Conception Evolution #227: Protect all connectors against reversed connection 0:30 Actions
FC005-ElectronicLoad 07/13/2020 François Cerbelle Conception Anomalie #234: Shift feedback from 0-5V to 0-0.075V 1:00 Actions
FC005-ElectronicLoad 07/11/2020 François Cerbelle Conception Evolution #195: Symetric power supply circuit 2:00 Actions
FC005-ElectronicLoad 07/10/2020 François Cerbelle Conception Evolution #195: Symetric power supply circuit 1:00 Actions
FC005-ElectronicLoad 07/08/2020 François Cerbelle Conception Evolution #230: Convert the whole resistor block use only -12/+12 (no 5V dependency anymore) 0:30 Actions
FC005-ElectronicLoad 07/07/2020 François Cerbelle Conception Anomalie #215: Security fan is currently progressively started 1:00 Actions
FC005-ElectronicLoad 07/07/2020 François Cerbelle Conception Anomalie #216: Add a second fan to balance current between -12/+12 and for better heat protection 2:00 Actions
FC005-ElectronicLoad 07/06/2020 François Cerbelle Conception Evolution #214: Convert the whole security block to use only -12/+12 (no GND/5V anymore) 1:00 Actions
FC005-ElectronicLoad 07/06/2020 François Cerbelle Conception Evolution #227: Protect all connectors against reversed connection 0:15 Actions
FC005-ElectronicLoad 07/06/2020 François Cerbelle Conception Evolution #229: Connect LM7805 to -12/+12 instead of GND/+12 0:15 Actions
FC005-ElectronicLoad 07/04/2020 François Cerbelle Conception Anomalie #205: Temperature value instability when sampling from ADC 1:00 Actions
FC005-ElectronicLoad 07/04/2020 François Cerbelle Conception Anomalie #224: Try heatsink insulation to avoid noise 0:15 Actions
FC005-ElectronicLoad 07/04/2020 François Cerbelle Conception Evolution #221: Use U10/D13 as ADC interrupt 0:15 Actions
FC005-ElectronicLoad 07/04/2020 François Cerbelle Conception Anomalie #223: fix Y1 crystal footprint 0:15 Actions
FC005-ElectronicLoad 07/04/2020 François Cerbelle Conception Evolution #226: LCD connector PCB silkscreen info 0:15 Actions
FC005-ElectronicLoad 07/04/2020 François Cerbelle Conception Evolution #219: Simplify voltage sense connector 0:15 Actions
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