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Overview

Meta-project with subprojects
Verilog playground for FPGA (Altera/Intel Cyclone family)
- SDRAM
- FIFO
- UART
- ...

Issue tracking

open closed Total
Anomalie 0 0 0
Evolution 10 0 10
Feature request 0 0 0

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Members

Manager : Fran├žois Cerbelle

Subprojects

fifo, uart