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# Project Tracker Status Priority Subject Assignee Updated Target version Estimated time % Done
318 Hakeva Anomalie Nouveau Normal Fix XT30 footprint François Cerbelle 04/11/2023 10:23 PM Hakeva - 0.1 1:00

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317 Hakeva Anomalie Nouveau Normal Improve MP4462 thermal dissipation with an heatsink François Cerbelle 04/11/2023 10:22 PM Hakeva - 0.1 1:00

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316 Hakeva Anomalie Résolu Normal Replace the NTMD3P03 dual PMOS with a FDS4935BZ because of thermal dissipation under 2A François Cerbelle 03/28/2023 03:44 PM Hakeva - 0.1 0:30

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315 Hakeva Feature request Nouveau Normal Add Clock François Cerbelle 03/22/2023 09:14 AM Hakeva - 0.1

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314 Hakeva Feature request Nouveau Normal Add SHA254 François Cerbelle 03/22/2023 08:46 AM Hakeva - 0.1

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313 Hakeva Feature request Nouveau Normal Add 10G SPF+ François Cerbelle 03/22/2023 08:45 AM Hakeva - 0.1

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312 Hakeva Feature request Nouveau Normal Add 10/100/1000 RJ45 François Cerbelle 03/22/2023 08:45 AM Hakeva - 0.1

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311 Hakeva Feature request Nouveau Normal Add PCIe connection François Cerbelle 03/22/2023 08:45 AM Hakeva - 0.1

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310 Hakeva Feature request Nouveau Normal Add eMMC François Cerbelle 03/22/2023 08:45 AM Hakeva - 0.1

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309 Hakeva Feature request Nouveau Normal Add DDR3 François Cerbelle 03/22/2023 08:44 AM Hakeva - 0.1

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308 Hakeva Feature request Nouveau Normal Add SPI Flash François Cerbelle 03/22/2023 08:44 AM Hakeva - 0.1

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307 Hakeva Feature request Nouveau Normal Add JTAG connector François Cerbelle 03/22/2023 08:44 AM Hakeva - 0.1

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306 Hakeva Anomalie Résolu Normal PowerSourceAutoSwitch: Fix Dual-NMOS footprint François Cerbelle 03/16/2023 08:00 PM Hakeva - 0.1 0:15

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305 Hakeva Anomalie Résolu Normal PowerSourceAutoSwitch: Update all components properties in schematic/PCB/BOM François Cerbelle 03/16/2023 07:59 PM Hakeva - 0.1 0:30

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303 Hakeva Feature request Résolu Normal Design the power switching between PCIe and ATX/XT30 François Cerbelle 02/26/2023 08:33 PM Hakeva - 0.1 2:00

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302 Hakeva Evolution Résolu Normal Design the first stage of power supply 12V −> 5.5V François Cerbelle 04/11/2023 10:25 PM Hakeva - 0.1 5:00

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301 Hakeva Evolution Nouveau Normal Update core design for a PCI card with DMA François Cerbelle 01/16/2023 08:35 AM Hakeva - 0.1 5:00

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300 Hakeva Evolution Nouveau Normal Rethink desing to have a FPGA PCB PCI formfactor compatible with PC and backplane François Cerbelle 01/15/2023 09:05 PM Hakeva - 0.1

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299 Hakeva Evolution Nouveau Normal Create a clean clock François Cerbelle 01/12/2023 08:47 AM Hakeva - 0.1 1:00

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298 Hakeva Evolution Résolu Normal Migrate design details from the documents to the wiki François Cerbelle 01/14/2023 11:03 AM Hakeva - 0.1 0:30

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297 Hakeva Anomalie Résolu Normal Make async reset safe regarding clock rises François Cerbelle 01/11/2023 11:23 PM Hakeva - 0.1

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296 Hakeva Evolution Nouveau Normal Change project id in Redmine and in Hg François Cerbelle 01/11/2023 08:08 AM Hakeva - 0.1

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295 Hakeva Evolution Résolu Normal Rename rediscore->gateware, redissoft->firmware, redispcb->hardware, FPGARedis->hakeva François Cerbelle 01/11/2023 11:23 PM Hakeva - 0.1 5:00

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294 Hakeva Evolution Résolu Normal Move all Verilog parameters in a configuration file to include François Cerbelle 01/11/2023 11:22 PM Hakeva - 0.1 0:15

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293 Hakeva Evolution Résolu Normal Switch everything to single clock domain in order to keep implementation simple for now François Cerbelle 01/11/2023 11:22 PM Hakeva - 0.1 2:00

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292 Hakeva Evolution Résolu Normal Use Active Low for control signals for better noise tolerance and ensure reset is active at powerup François Cerbelle 01/11/2023 11:21 PM Hakeva - 0.1 2:00

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291 Hakeva Feature request Nouveau Normal Implement UART François Cerbelle 02/09/2023 09:05 AM Hakeva - 0.1 5:00

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290 Hakeva Feature request Résolu Normal Implement FIFO François Cerbelle 01/11/2023 08:38 AM Hakeva - 0.1 3:00

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289 Hakeva Feature request Résolu Normal Implement SyncW/AsyncR DP-SC in RAM module François Cerbelle 01/10/2023 09:30 AM Hakeva - 0.1 1:00

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245 Firmware Anomalie Nouveau Normal Serial datalogger (FTDI/Openlog) 07/09/2020 06:10 PM Firmware - 1.0

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244 Firmware Anomalie Nouveau Normal Save/Load/Reset settings in EEPROM 07/09/2020 06:10 PM Firmware - 1.0

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243 Firmware Anomalie Nouveau Normal USB programmation and monitoring 07/09/2020 06:09 PM Firmware - 1.0

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242 Firmware Anomalie Nouveau Normal Trigger (start, stop, pattern) 07/09/2020 06:09 PM Firmware - 1.0

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241 Firmware Anomalie Nouveau Normal Current, Voltage, Power, Resistance control modes 07/09/2020 06:09 PM Firmware - 1.0

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240 Firmware Anomalie Nouveau Normal External temperature sensors + protection (pause or stop) 07/09/2020 06:09 PM Firmware - 1.0

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239 Firmware Anomalie Nouveau Normal OverPower protection 07/09/2020 06:08 PM Firmware - 1.0

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238 Firmware Anomalie Nouveau Normal OverCurrent protection 07/09/2020 06:08 PM Firmware - 1.0

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237 Firmware Anomalie Nouveau Normal OverVoltage protection 07/09/2020 06:08 PM Firmware - 1.0

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236 Firmware Anomalie Nouveau Normal UnderVoltage protection (Cut-off for batteries) 07/09/2020 06:08 PM Firmware - 1.0

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266 fifo Evolution Nouveau Normal fifo testbench 08/20/2020 01:09 PM fifo - 1.0

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265 fifo Evolution Nouveau Normal signal testbench 08/20/2020 01:09 PM fifo - 1.0

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264 fifo Evolution Nouveau Normal raddr testbench 08/20/2020 01:09 PM fifo - 1.0

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263 fifo Evolution Nouveau Normal waddr testbench 08/20/2020 01:09 PM fifo - 1.0

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262 fifo Evolution Nouveau Normal buffer testbench 08/20/2020 01:04 PM fifo - 1.0

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261 fifo Evolution Nouveau Normal signal submodule 08/20/2020 01:12 PM fifo - 1.0

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260 fifo Evolution Nouveau Normal fifo_overflow port in fifo module 08/20/2020 01:12 PM fifo - 1.0 1:00

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259 fifo Evolution Nouveau Normal fifo_full port in fifo module 08/20/2020 01:12 PM fifo - 1.0 1:00

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258 fifo Evolution Nouveau Normal fifo_underflow port in fifo module 08/20/2020 01:12 PM fifo - 1.0 1:00

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257 fifo Evolution Nouveau Normal fifo_empty port in fifo module 08/20/2020 01:12 PM fifo - 1.0 1:00

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147 Raspberry Pi Cluster Evolution Résolu Normal Add Watchdog in initramfs 08/22/2015 08:33 PM Raspberry Pi Cluster - 1.1 1:00

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